The Universal Serial Bus (USB) 2.0 standard supports data transmission rates of 1.5, 12 and 480 megabits per second. The data can be transmitted over cables up to 5 m in length and up to 127 devices can be supported. A USB 2.0 host controller is required to control the bus and the data transfer. FIG. 1 shows the circuit connection of a USB mass storage bridge controller in a computer system. A computer 102 has a USB host controller inside of the computer. The host controller controls the transmission along the USB bus 104 to the USB mass storage bridge controller 106. The USB mass storage bridge controller 106 is connected via an ATA/ATAPI bus 108 to an ATA/ATAPI mass storage drive 110. This can be, for example, an ATA hard drive or an ATAPI CD or DVD drive. The USB host controller sends a command block wrapper (CBW) data packet along the USB bus as shown in block 112. This signal is used by the USB mass storage bridge controller 106 to program the drive 110 to receive or send data. As shown block 112, data transfer then takes place between the computer and the mass storage drive or between the mass storage drive and the computer. Once the data transmission has been completed, a Command Status Wrapper (CSW) data packet showing the status of the drive and of the data transmission is sent back to the computer. USB 2.0 supports two types of transfers for large blocks of data: a bulk transfer for moving data that cannot tolerate errors and an isochronous transfer for moving data that cannot tolerate delay. The transport command set used in the bulk-only protocol is based upon the SCSI transparent command set, which is wrapped with certain information related to the bulk-only protocol, to form a command block wrapper (CBW) for a specific transport.
The CBW contains 31 bytes of data which must be processed. Certain bytes are checked for authenticity whereas others are utilized to program the device from/to which the data transfer will occur. Table 1 shows of an arrangement of a Command Block Wrapper (CBW). The first field contains 4 bytes of data corresponding to the dCBWSignature which identifies the data packet as a CBW. The next field is the command block tag which is sent by the host. The contents of this field are echoed back to the host when the drive returns the status packet (CSW). The third field containing bytes 8–11 is the data transfer length and contains the number of bytes of data that the host expects to transfer on the bulk-in or bulk-out transfer during the execution of the command. If this field is zero, the drive and the host transfer no data and the device will ignore the value of the direction bit. The next field comprises byte 12 which contains the CBW flags which controls the direction of data transfer. The next field contains a single byte which has the first 4 bits reserved and a second 4 bits containing the logical unit number of the device to/from which data is transferred. The next field contains 3 bits which are reserved and five bits used for the command block length. The final field contains bytes 15–30 which contains the command block which is the command to be executed by the drive.
Typically the processing of the CBW has been accomplished by using a hardware state machine or by using a software controlled microcontroller (MCU). The hardware state machine is much faster than a software controlled microcontroller and can typically perform this task in a few microseconds. The disadvantage of a hardware state machine based device is that it is not adaptable to ATA/ATAPI devices which may not correctly follow the standard. Manufacturers may choose to use reserved registers to provide additional features in their device. This is a common situation. This means that an existing hardware state machine based controller cannot be used with non-compliant devices because it cannot handle the nonstandard situation. Once the hardware controller is manufactured in silicon, it is not possible to change the operation of the state machine. A software controlled microcontroller, however, can readily be changed because the software program is normally stored in an electrically reprogrammable non-volatile memory, such as flash memory or EEPROM, to provide the needed flexibility to handle a later produced non-standard device. A software solution, however, is much slower than the hardware solution and typically takes 500–700 microseconds to perform the task.
Table 1Command Block WrapperbitByte765432100–3dCBWSignature4–7dCBWTag 8–11dCBWData TransferLength(08h-0Bh)12bmCBWFlags(0Ch)13Reserved (0)bCBWLUN(0Dh)14Reserved (0)bCBWCBLength(0Eh)15–30CBWCB(0Fh-1Eh)
The USB 2.0 bus is a convenient way to add additional storage capacity to a computer, especially a laptop computer, and USB 2.0 connected hard drives are readily available. Tests utilizing standard benchmark software for such devices show that they are slower than internal hard drives. The 500–700 microseconds time required by the software based controller to set up the data transfer is the same regardless of the size of the file transferred. Thus, it appears that this time seriously impacts the performance of USB 2.0 connected hard drives. Therefore, there's a need for a USB 2.0 controller that has the speed of a hardware state machine and the flexibility of a software controlled microcontroller and in addition can perform the operation at a higher speed than currently available devices.